1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit in which a terminal to be connected to an oscillator is used also as input/output terminal for signals.
2. Description of Related Art
FIG. 1 is a circuit diagram showing a structure of such a semiconductor integrated circuit in the prior art. A chip A containing a semiconductor integrated circuit is provided with external terminals 1 and 2. The chip A contains an NAND circuit 5, i.e., an inverting and amplifying circuit which is formed of a CMOS transistor using as its power supply an output of an unillustrated voltage reducing regulator reducing a voltage. The external terminal 1 is connected to an input terminal at one side of the NAND circuit 5, of which output terminal is connected to the external terminal 2 and an unillustrated circuit to which a clock is to be supplied.
The NAND circuit 5 receives on its input terminal at the other side a state-switching control signal 9 for switching the state of an oscillator circuit, which will be described later, between an active state and an inactive state. A damping resistance 6 and an oscillator 8 are connected in parallel between external terminals 1 and 2. The external terminals 1 and 2 are grounded via respective load capacitances 7. In this manner, a low power consumption oscillator circuit is formed of the NAND circuit 5, damping resistance 6, load capacitances 7 and oscillator 8.
Then, operation of the semiconductor integrated circuit will be described below. When the state-switching control signal 9 is set to the H-level, the NAND circuit 5 operates as an inverting amplifier, and the oscillator 8 oscillates owing to the damping resistance 6 and the load capacitance 7.
When the state-switching control signal 9 is set to the L-level, the output of NAND circuit 5 attains the H-level regardless of the input, from the external terminal 1, and the oscillator 8 does not oscillate any longer. In this manner, the external terminals 1 and 2 function as terminals for connecting the oscillator 8.
The semiconductor integrated circuit described above may be provided with terminals for connecting another oscillator circuit having a different oscillation frequency. FIG. 2 is a circuit diagram showing a structure of such a semiconductor integrated circuit. The chip A containing the semiconductor integrated circuit is provided with external terminals 31 and 32 for an oscillator circuit having an oscillation frequency of A(Hz) and external terminals 33 and 34 for an oscillator circuit having an oscillation frequency of B(Hz), and contains an inverting amplifier, i.e., NAND circuit 35, an NAND circuit 36 and a system clock select switch 38.
The external terminal 31 is connected to an input terminal at one side of the NAND circuit 35, and the NAND circuit 35 receives on its input terminal at the other side an oscillation control signal 37 from an oscillator circuit of an oscillation frequency of A(Hz). An output terminal 91 of the NAND circuit 35 is connected to the external terminal 32 and the one terminal 38a of a system clock select switch 38. The external terminal 33 is connected to an input terminal at one side of the NAND circuit 36, and the NAND circuit 36 receives on its input terminal at the other side an oscillation control signal 39 from an oscillator circuit of an oscillation frequency of B(Hz). An output terminal of the NAND circuit 36 is connected to the external terminal 34 and the other terminal 38b of the system clock select switch 38.
A switching terminal 38c of the system clock select switch 38 is connected to an unillustrated circuit to which a clock 40 is to be applied. A damping resistance 41 and an oscillator 42 of an oscillation frequency A(Hz) are interposed in parallel between external terminals 31 and 32, each of which is grounded via a load capacitance 43. A damping resistance 44 and an oscillator 45 of an oscillation frequency B(Hz) are interposed in parallel between external terminals 33 and 34, each of which is grounded via a load capacitance 46.
According to the semiconductor integrated circuit thus constructed, while the oscillator (e.g., oscillator 45) is oscillating, the other oscillator 42 can stop its oscillation, and the external terminals 31 and 32 connected to the stopped oscillator 42 attain the state performing no function. FIG. 3 is a timing chart showing various signals.
If the external terminal (e.g., terminal 32 as described above) in the state performing no function is to be used for input/output of a signal, such a structure may be used that a transfer gate TF is interposed between the NAND gate 35 and the one external terminal 32 as represented by broken line, and a circuit which connects the transfer gate to the one external terminal 32 is connected to the input of the input buffer 3 and the output of the output buffer 4 as represented by broken line. According to this structure, the oscillation is enabled when the transfer gate TF is turned on. Also, when the transfer gate TF is turned off, the loop of the oscillator circuit is disconnected, and the input buffer 3 or the output buffer 4 can input or output the signal, so that the external terminal 32 can be used as the input/output terminal. However, the resistance Rt of transistor of the transfer gate can be substantially expressed by the following formula: EQU R.sub.t =1/(.beta.(V.sub.GS -V.sub.th -V.sub.DS)) (1) EQU .beta.=(.mu..epsilon./t.sub.OX)(W/L) (2)
where (at unsaturated region)
.mu.: effective surface mobility of electrons at channel PA1 .beta.: gain coefficient of MOS transistor PA1 .epsilon.: dielectric constant of gate insulator PA1 V.sub.GS : voltage across gate and source PA1 V.sub.th : threshold voltage PA1 V.sub.DS : voltage across drain and source PA1 t.sub.OX : thickness of gate insulator PA1 W: channel width PA1 L: channel length
As can be seen from the above formulas (1),(2), the resistance Rt of transistor of the transfer gate increases in accordance with decrease of the power supply voltage, and forms a large load against the drive capability of the oscillator circuit, which narrows a low voltage region, i.e., a region allowing the oscillation. Therefore, if the transistor having the conventional transistor characteristics is used at the transfer gate, it may be impossible to ensure turn-on at the start of the oscillation because the on-resistance of the transfer gate is high.
Thus, when the function-switching control signal 90 attains the H-level as shown in FIG. 3, the transfer gate TF is turned on. However, the on-resistance of the transfer gate TF does not, decrease as described before. Therefore, the oscillation may not be performed, in which case the oscillation voltage is not applied to the output terminal 91 of the NAND circuit 35 and the external terminal 32 as shown in FIG. 3. Thereafter, when the function-switching control signal 90 attains the L-level as shown in FIG. 3, the transfer gate TF is turned off. When the output control signal 10 attains the H-level as shown in FIG. 3, the signal 92 is sent to the external terminal 32 via the output buffer 4. Although the state can be surely switched from the oscillating state to the signal input/output state, the state may not be surely switched from the signal input/output state to the oscillating state.